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Designing a Better PCB:We are constantly pushing ourselves for better printed circuit boards (PCB). One thing we've learned is that PCB fab houses (such as Advanced Circuits, BatchPCB, PCB123, Gold Phoenix, Bare Bones PCB, anyone really) have a very hard job to do. Creating a PCB is not an easy task and there are many ways for a fab house to mess it up. Unfortunately, fab houses tend to spend less time on prototypes than on production runs. Therefore, we try to design products and PCBs for 'manufacturability'. This tutorial will show you how to minimize the number of ways the fab house can screw up a PCB.We've messed up piles of PCBs over the years. We want to share with you some of the DFM (design for manufacture) rules and tricks and tips we've learned to get a good PCB, every time. If you're creating a prototype PCB, we highly recommend you use these rules to increase the chances that your proto will work! Important Files:
Trace Width and Spacing: Just because a fab house can handle down to 5mil traces and 6mil space doesn't mean you should design with those sizes. If your board can be routed with 10mil traces and 10mil spaces, do it! The smaller you make things, the more likely you will get a PCB with broken trace (traces less than 10mil) or two traces touching each other (less than 10mil spacing between traces).  PIC32 development board Even complex boards with tight pitch packages and a horrible rat's nest of traces can be routed with 10mil traces and 8mil spacing. Next time you route a board, try it with 10mil traces and see just how far you can go - you'll be suprised. If things get really tough, 8mil is usually ok. The goal of all these tricks and rules is the limit the spots where manufacturing failures could occur. A ground (or power) plane is a good idea on some projects. But a plane (sometimes called a polygon plane) increases the odds of the plane being mistakenly 'poured' onto a trace.  What the?! Bad ground pour. Bad!  A simple board with 10mil isolation  Increased isolation good, ground plane break may be bad. To increase the isolation on an existing polygon, click on the 'i' button for information, then click on the border of the polygon.  Then change the Isolate from a default of 0.010 to 0.012. Annular Ring: Another problem that we have found is sloppy drill hits by a fab house. To connect a trace from one side of the PCB to the other, we use a via. A via is composed of a drilled hole, two circles of copper larger than the hole on either side of the board, and connecting copper inside the hole to connect the circles on either side of the board (these are called plated through holes). Vias make PCBs work. The problem is the size of the copper circles. If the drill hit is not in the middle of the circles, the drill hole can potentially break the via and the trace connected to the via.  Sloppy drill hits in the center of the vias All of the vias shown above work, but they are marginal. This is one board out of a run of many and the other boards could be even worse. If the drill hit is too far off center, it can cut through the trace connecting to the via. To help protect against this, we increase the size of the annular ring around the vias. To do this, we edit the Eagle DRC rules (click on menu Tools->DRC).  Restring tab of the Eagle DRC rules Click on the tab labeled 'Restring'. The default for pads on the top and bottom is 10mil. We change this to 12 mil to increase the annular rings by 20%. This will increase the chances that our prototype PCB will work. This DRC setting is set to 12mil in the SparkFun DRC file. Generating good gerber files of your PCB is the final step that causes many people to fail. Eagle uses a CAM file to create the gerber files to have a PCB made. We have seen tons of people create horribly defective gerber files. Please start with our CAM file - and modify if you really need to. We've used this CAM file thousands of times without problems. We've changed the default Eagle CAM file so that it does not mirror any of the bottom layers (number one problem with gerber submissions!), it outputs a standard Excellon drill file (second most common error is a missing drill file), and captures only the tPlace layer onto the silkscreen layer (this will cause all part identifiers and values to not print on the silkscreen). Put all text and labels onto the tPlace layer that you want to see printed on the board. Tenting: Tenting refers to the soldermask and vias. The vias on a board may be left exposed or covered up by the soldermask. We've found that covering up the vias (or 'tenting' them) decreases the chances that the silkscreen labels will be broken and gives the overall board a much better look. Don't worry, you can still probe a tented via for voltage and continuity with a multimeter - the soldermask will break down when you insert the probe into the hole. However, it will be much more difficult to solder to a tented via.  Untented vias. Ugly silkscreen. Small 10mil isolation on plane. The bottom of the FT245RL breakout is shown above. The pin labels are completely un-readable because an untented via falls right in the middle of 'WR' and 'RE'. Is that 'RE'... I can't remember.  Tented vias. Happier silkscreen. 12mil isolation on polygon pour. Bottom view of the XBee-Explorer product. I have been known to move a via to avoid a label as well, but that's just me. Tenting is taken care of in Eagle by modifying the DRC rules. To see if the vias will be tented or not, turn on all the layers by clicking on the display button:  The Display button is below the 'i' button.  Click on 'All' then OK.  To tent your vias, open the DRC rules on your current design (Tools->DRC menu).  DRC Rules - Masks tab Then increase the limit value to larger than the vias you are using. For instance, if the vias on your board are the default 0.023mil, then change the limit to 25mil and all drill hits under 25mil (0.025) will be covered in soldermask. Be careful! Don't set this number too high or you will cover important holes, like those meant to solder on connectors. The DRC setting is set to 25mil in the SparkFun DRC file. Label everything, all the time: This is another cosmetic issue I see so often it hurts. You should label every button, switch, LED, pin, and especially power connectors on your board. Every one of them!  Labels! They are so easy, but so often overlooked.
I personally do not put any part indicators on my boards. When assembling the board, sure, I need to know where the 10k resistors go, the 0.1uF caps, and the LED colors. But that's all part of the assembly sheet. Once the device is built, I most likely will never need to know that a given capacitor is '22pF' and certainly I don't need to know that the big IC on the board is labeled 'U1' (what help is that anyway?). If I'm really troubleshooting a board, I will have the schematic and layout open anyways. On the flip side, it would be nice to know what the pin functions are - right there, clearly labeled, so I don't have to guess. Every time I connect power, it would be really nice not to say a prayer and hope I don't hook power up backwards. And if I do hook power up backwards, is that LED supposed to come on? Or is that just a link connection LED? Oh shoot!  The ADXL330 Breakout Here is a good example of clear pin labels as well as worthy functional labels. When playing with this accelerometer, you will probably want to know what axis is where. Yes, you could look up the datasheet but why not put the information right there on the board? We hope these basic rules help you prevent as many mistakes as possible! We certainly have our share of coffee coasters and hope you have one less. Cheers! Nathan Seidle |
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thanks for the tutorial
Once again, you guys freely impart another chunk of hard earned wisdom for the betterment of the public.
Thank you for the tutorial. I will put it to good use.
Jeronimo
www.blogdoje.com.br
Arduino, Avr & ARM
I'd like to know more about BatchPCB Outline and the Mill job in the CAM.
BatchPCB allows me to upload a "outline" file. Can you give us some hints how to generate such a file ?
The Eagle CAM file mentioned above generates a .GML file which uses the "Milling" layer (46) in Eagle. For the outline i'd expect it to generate a file based on "Dimension" (20).
Also, previous tutorials mentioned using a cleaned up version of the silkscreen "_tPlace" (121) (generated after running "silk_gen.ulp"). The script removes silkscreening on solderable areas. This tutorial doesn't mention it and the CAM uses the "tPlace" (21) only. In the pictures I see pin labels, do you add other layers to the silkscreen as well ?
Thanks again, Ivo
It's very important that you have some sort of an outline for your board. Using our CAM file, the Dimension layer will be outputted to the top copper layer. Sounds odd that the PCB border should be in copper, but here at SparkFun/BatchPCB, we really just need some indicator of where your board border is. Top Silk is also an acceptable place for your border.
We do not use, and I do not recommend using, the silk_gen.ulp. We only use our CAM file to generate the correct silk. This works because I do not want part indicators or values to print on my PCBs.
Oh - always always remember to turn on vector fonts! (http://www.sparkfun.com/commerce/tutorial_info.php?tutorials_id=109)
If you change the isolation to 12mil that is sufficient to break pours that occur between standard 0.1" headers. This may or may not affect your board. I have also never seen a problem yet from Gold Phoenix (used by batchpcb). In fact if you receive a board with a pour into a signal, I would suggest you return it and ask for a replacement because that is sloppy quality control.
Because Gold Phoenix can do down to 7mil for a two-sided board it shows that their masks have quite good resolution. Some other low cost manufacturers can only do 10 mil and these are the ones I would be more concerned about.
My personal preference is not to tent the vias, especially if it is a prototype board. This is because I sometimes use the vias to help with testing.
I also either move the via or silkscreen to ensure that the silk screen is not over a hole.
Has anyone had luck with Tented Vias when using Advanced Circuits (www.4pcb.com)? Their www.FreeDFM.com web site says they can't fix (to their liking) tented vias...
Thanks,
- Steve
Where can I see complete table for these values?
Here's a concern: Your SF Design Rules say to use a 0.05 inch grid. But for the DFN design I did recently I found that I needed to use Metric (millimeter) mode to be able to define my footprint and to place and route it correctly. Would this be a violation of your design rules? I used 0.2mm line and space rules for routing - slightly under 8 mil. The boards I got back were perfect as near as I could tell.
What guidance would you have for future similar designs?
Thanks.
Less than 2 files found! Something is missing, please check your upload package.
I am using kicad...
All of the gerber files look ok in a viewer I zipped them in windows and ubunu before nether worked.
I put a date code in the bottom copper layer, but the BatchPCB robot rejected the board. I've changed it to a larger graphical date code (boxes for year, circles for board version). Perhaps a macro could encode the date in some standard (in the community) representation?
Also, how do you set the default trace width? These 8 mil traces seem a little small, but I don't want to replace every individual trace segment.
Thanks again! SparkFun rocks!
Set WIRE_BEND 1; #Route with 45 degree angles
Set Drill 0.02; #Make vias 0.02"
Change Shape Round; #Make vias round
Change Width 0.01; #Routing width default to 10mil