Xilinx Design Summary

TUTORIAL Partition Summary
No partition information was found.

Device Utilization Summary
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	11	4,896	1%
Number of 4 input LUTs	4	4,896	1%
Logic Distribution
Number of occupied Slices	7	2,448	1%
Number of Slices containing only related logic	7	7	100%
Number of Slices containing unrelated logic	0	7	0%
Total Number of 4 input LUTs	11	4,896	1%
Number used as logic	4
Number used as a route-thru	7
Number of bonded IOBs	9	158	5%
Number of GCLKs	1	24	4%
Total equivalent gate count for design	157
Additional JTAG gate count for IOBs	432

Performance Summary
Final Timing Score:	0	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met