"id","sku","name","description","description_markdown","date_published","price","qty_price","in_stock","backorder_allowed","is_rohs_compliant","is_export_controlled","is_oshw","in_eagle_library","in_fritzing_library","sparkfun_original","hstariff","pack_length","pack_width","pack_height","packed_weight","ascii_art","ascii_art_url","categories","quantity","images","videos","related_products"
"10109","COM-10109","XMOS Processor - XS1-L1-64","
The XS1 family of devices features a multi-threaded processor architecture constructed from XCore processors connected by communication links. The architecture is scalable and any number of XCore processors can be connected together.
Applications are developed using a combination of XC, C, and C++. XC provides extensions to C that simplify the control over concurrency, I/O and time. These extensions map directly to XS1 device resources making it easy to write embedded applications that require a blend of control code, DSP, and interfacing.
Features:
- Event driven processing at 400MIPS
- 64 kBytes of SRAM
- 8 threads
- 36 user I/O pins
- 8 kBytes of OTP memory for application boot code and security keys
- A typical power consumption of 450µW/MHz
Documents:
- [Datasheet](http://cdn.sparkfun.com/datasheets/Components/General IC/XS1-L01A-LQ64-DatasheetX1135C.pdf)
- [I/O Timing](http://cdn.sparkfun.com/datasheets/Components/General IC/XS1-Port-I-O-TimingX5821A.pdf)
- Example Code
- XMOS Website
- XCore
","The XS1 family of devices features a multi-threaded processor architecture constructed from XCore processors connected by communication links. The architecture is scalable and any number of XCore processors can be connected together.
Applications are developed using a combination of XC, C, and C++. XC provides extensions to C that simplify the control over concurrency, I/O and time. These extensions map directly to XS1 device resources making it easy to write embedded applications that require a blend of control code, DSP, and interfacing.
**Features:**
* Event driven processing at 400MIPS
* 64 kBytes of SRAM
* 8 threads
* 36 user I/O pins
* 8 kBytes of OTP memory for application boot code and security keys
* A typical power consumption of 450µW/MHz
**Documents:**
* [Datasheet](http://cdn.sparkfun.com/datasheets/Components/General IC/XS1-L01A-LQ64-DatasheetX1135C.pdf)
* [I/O Timing](http://cdn.sparkfun.com/datasheets/Components/General IC/XS1-Port-I-O-TimingX5821A.pdf)
* [Example Code](http://www.sparkfun.com/datasheets/DevTools/XMOS/SFE_Example.zip)
* [XMOS Website](https://www.xmos.com/en/published/xc_en)
* [XCore](http://www.xcore.com/)
","2010-08-30 11:27:32-06","7.95","7.957.557.16","","","1","1","","","","","","60mm","25mm","2mm","0.0016lbs","
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","https://www.sparkfun.com/products/10109/images.txt","PTH ICs","0","","",""