Creative Commons images are CC BY-NC-SA 3.0

79.95

added to your
shopping cart

quantity
In stock 79 in stock
79.95 1+ units
71.96 10+ units
63.96 100+ units

Description: The Mojo Clock/Visualizer Shield is a simple add-on for the Mojo v3 FPGA development platform. This shield's primary purpose is to give you with a great way to get started with FPGA (Field-Programmable Gate Array) development by providing an easy to set up real-time clock and audio visualizer. This shield is equipped with two 8x8 RGB LED matrices with full 24 bit color that connect directly to the Mojo's I/O pins and a microphone and light sensor that connect to the Mojo's analog inputs. 

With the example design listed below this shield will quickly become a basic real-time clock. Setting the time is easy, just hold the select button until the hour flashes, using the up and down buttons to adjust the hour  and select again to edit the minutes. Then you're done, press select to set the time! Additionally, the light sensor attached to the shield is capable of detecting the ambient light levels to adjust how bright the RGB LED matrices get, that way you won't have to worry about a plethora of colors bothering you while you try and sleep.

The Clock/Visualizer Shield's built in microphone you'll be able to capture music or sounds transforming the clock into an audio visualizer. 1024 samples are taken from the microphone on each new frame and fed into through a FFT with the lowest 16 values shown on the display. The visualizer has two modes, the basic mode with just the green, yellow, and red bars, as well as the rainbow mode, where a rainbow pattern flows over the display utilizing the shields full 24 bit color.

Features:

  • 2x 8x8 RGB LED Matricies with diffused lenses
  • 3x Push buttons (Up, Down, and Select)
  • DS3234 RTC (Real-Time Clock) with 256 bytes of battery backed SRAM
  • 12mm coin cell battery to backup the RTC
  • Buzzer
  • TEMT6000 Light sensor
  • ADMP421 Microphone

Documents:

Comments 1 comment

  • A couple notes for everyone on the Example Design:

    1. The project was made in 14.4. The last version of ISE is 14.7, and I STRONGLY suggest you upgrade it to 14.7.
    2. if you upgrade to 14.7, you WILL have to upgrade the IP. This might potentially break the HDL, so be careful.

    And as a bias point, I recommend migrating to PlanAhead. This way, if you want to move it to a Nexys4 or other Xilinx 7-series/Zynq parts, it can be done very easily.


Related Products