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Xilinx SmartLynq+ Module is intended for high-speed debug and trace, primarily targeting designs using the Versal™ platform. The SmartLynq+ Module delivers up to 28X faster configuration time via a high-speed debug port (HSDP). The SmartLynq+ Module has advanced configuration throughput performance to accelerate the development cycle. The Module supports both serial and parallel trace with up to 14GB of trace memory to capture a design execution history.
The Xilinx SmartLynq+ Module is compatible with Versal ACAP evaluation boards. Users have complete visibility to the Versal™ architecture, including AI Engines, programmable network on chip (NoC), DDR memory controller, and 100G multirate Ethernet cores.
Furthermore, smart filtering with a software customizable built-in debugger facilitates remote access and sharing. The SmartLynq+ Module is an ideal debug and trace platform, enabling fast configuration, extensive trace capture, high visibility, and flexibility.
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