Retired Product

This product has been retired from our catalog and is no longer for sale. This page is made available for those looking for datasheets and the simply curious.

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Description: The LogicStart is an open source MegaWing for the Papilio Pro development platform that provides you with everything you need to get started with VHDL (VHSIC [Very-High-Speed Integrated Circuits] Hardware Description Language) and FPGA development. This is the perfect MegaWing if you are just starting out with FPGA. Once paired with your Papilio board, the Logic Start provides you with many ammenities for experimenting and learning about FPGA development!

MegaWings are FPGA add-ons that plug straight into a Papilio Pro board and provide everything needed for a specific application in one convenient PCB. Since this LogicStart is a MegaWing it won’t work on it’s own so make sure you have, or pick up a Papilio Pro, if you want to learning how to develop in an FPGA or VHDL environment.

The LogicStart MegaWing comes equipped with a VGA video port, a seven segment display, 1/8th" mono audio jack, a 5-way micro joystick, an SPI ADC with an ADC128S102 IC, and 8 slide switches with status LEDs. If you are looking for a little help with your new FPGA the LogicStart MegaWing is a great place to begin!

Features:

  • 7 Segment Display - 4 Character
  • VGA Port - 3r,3g,2b VGA Output
  • Mono Audio Jack - 1/8" Jack, Low Pass Filter, Delta Sigma DAC
  • Micro-Joystick - 5 directions
  • SPI ADC - 12-bit, 1Msps, 8 Channel
  • 8 LED’s - User Feedback
  • 8 Slide Switches - User Input

Documents:

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Customer Comments

  • About the only negative thing I can say about this nice board is that it was poorly washed by the manufacturer. It was quite sticky with flux residue, enough to make me clean it before using it. Intro to Spartan FPGA follows the Papilio One + LogicStart so closely that it makes it super easy to follow along. If you run into an issue with the first project not displaying anything on the LEDs, remember to SAVE and CLOSE your constraints file before synthesizing. Xilinx will happily synthesize and implement your design without actually using your constraints file, meaning that your inputs/outputs will not be on the right pins.

  • The pin mapping for use with the Papilio One and Papilio Pro can be found on http://papilio.cc/index.php?n=Papilio.LogicStartMegaWing

  • A few things to remember about addons to the Papilio that many people over look.

    1. VHDL is not the only language you can use for this. Verilog is just as good.
    2. FPGAs have things called, “IO Standards” which to most make very little sense. These standards basically tell the FPGA how signals will come in/out of the chip. From the looks of the schematic, everything is set for LVCMOS33. This is the Low Voltage CMOS 3.3V standard. When you are about ready to push your code to the FPGA, make sure your IO are set to this in order for it to be okay.
    3. Read the datasheets of the Wings whenever possible. These should be providing information on how to properly interface.

    To the Catalog Monkey. Please make a link to the UCF file provided for the wing.

    • We try not to link to files that will be changed and revisioned. the UCFs will change over time, making our links outdated. I was able to download them without issue at all.

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