AndyP

Member Since: July 12, 2007

Country: United States

  • If you read the HX711 data sheet, you'll see that it specs a range of 2.7 V to 5.5 V for DVDD and VSUP. So there is no reason why you can't use single 3.3 V supply for both VCC and VDD with this board.

    HOWEVER -- read that data sheet again. There is a statement: "When using internal analog supply regulator, the dropout voltage of the regulator depends on the external transistor used. The output voltage is equal to VAVDD=VBG*(R1+R2)/ R1 (Fig. 1). This voltage should be designed with a minimum of 100mV below VSUP voltage."

    (Also, as commenter Member #461211 points out below, the data sheet is wrong -- the denominator should be R2, not R1, and the SparkFun schematic reflects that.)

    100 mV is the dropout spec for the HX711's regulator.

    So do the math, and AVDD with the resistor values on the board is 4.3 V. With a 5 V VCC, the drop-out spec is easily met. But, obviously with a 3.3 V VCC, there's no way this will work, so you need to adjust the feedback resistors on the board to something that is acceptable. Change R1 from 20k to 11.5k and AVDD becomes 3.0 V, which is obviously 300 mV below the input 3.3 V and it also meets the dropout spec, and the HX711 should work just fine and give you reasonable conversion results.

  • I know that F360 "doesn't operate in the manner, in which I described," hence the question: do you have a proper 3D model?

    Anyway, I created one. Use at your own risk. it's here

    I should have just bought the Bournes encoders I originally specified -- Bournes provides models.

  • Yeah, I figured as much. The dimensional drawing is nice but I can't import it into Fusion 360. The manufacturer of the part, Top-Up, doesn't have any 3D models on its website.

    But it turns out that these parts are copies of the TE Connectivity DPL12 parts (https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Data+Sheet%7F1-1773449-0%7FG%7Fpdf%7FEnglish%7FENG_DS_1-1773449-0_G.pdf%7F2-1879314-1) and TE provides models.

    (edit: not an exact copy! Dang it!)

  • This is possibly a ridiculous request, but is a 3D model of this part available? Its pins fit into the footprint of the Bournes PEL12T devices but the body is slightly different.

  • I've designed several products with the THAT1646 (and the TI equivalent, the DRV134) and the part is great. But there is an important caveat noted in the datasheet, under Applications on page 6:

    "2. Both devices must be driven from a low- impedance source, preferably directly from opamp outputs, to maintain the specified performance."

    Look at the part's internal schematic. It has a moderate input impedance, 5kΩ. The pin labeled "GND" really isn't a power-supply return pin, it is just a side of another 5kΩ resistor whose other side goes to the op-amp's input. The op-amp inside the 1646 is configured as a non-inverting amplifier, so if you look at the common configuration for such an op-amp, you'll see that this second resistor is the Rin part of the feedback network.

    What does this mean? It means that if you drive it from a source without low-impedance drive, such as the wiper of a pot, the balance is wrecked. The result is asymmetrical drive, and that asymmetry is a function of the source impedance. This asymmetry might not be a problem in many applications where the connected receiver is a differential amplifier (THAT1200-series, INA217, or a diff-amp built from a pair of op-amps, or a transformer) and in circuits with the standard ±15 V rails and standard line-level (+4 dBu) audio. But if you power the 1646 from reduced rails, like its ±5 V lower limit, you'll clip easily.

    So you definitely want to drive this guy with an op-amp.

  • Comments on your comments: Rise and fall times have nothing to do with setup and hold time.

    Rise and fall time tell you how fast the driver can transition a signal from one logic state to the other. The main reason to be concerned about these times is so that a signal doesn't linger at an "undefined" level between valid logic states. This causes odd switching and can be a real problem on clock signals. Also, the faster the rise/fall time, the more you have to worry about signal integrity and termination and all of that. Note that rise and fall times are not special to SPI; they apply to ALL digital logic signals, synchronous or not.

    Setup time indicates when a data signal needs to be stable before a clock edge. Hold time indicates how long a data signal needs to remain stable after a clock edge. These parameters are critical for all synchronous logic circuits, including not only flip-flops but also synchronous memory elements (RAMs, ROMs, FIFOs). If it's got a clock, it's got setup and hold-time requirements.

    So the waveform displays which exaggerate the effect of rise and fall time and show you 10% and 90% levels are nice, but in the real world you just measure timing at the middle of the transition.

    Note that there's a reason why SPI clocks data out on one edge and clocks it in on the other. It's so you don't have to deal with setup and hold time and driver clock-to-out calculations at all.

    Consider what some might call a "fast" SPI bus, with a 20 MHz (50 ns period) clock. Say the receiver has a setup time spec of 2 ns and a hold time spec of 2 ns. Say the driver has a clock to out time of 1 ns. If the driver and receiver were clocked on the same edges, then at clock edge 0, 1 ns later the data line transitions. At the same edge, the receiver looks at the input. Now a 1 ns clock-to-out means the signal is stable at the receiver 49 ns early (easily meeting setup) BUT it failed to meet hold time since it changed 1 ns after the clock but hold time says the receiver needs it stable 2 ns after the clock.

    Now clock in on the rising edge and out on the falling edge. 1 ns after the falling edge, the signal transitions (clock to out delay). With 2 ns setup time required at the receiver, you have 22 ns of slack (period - requirement - clock-to-out). Also, the signal is held at the receiver for 26 ns after the rising edge so you can't fail hold-time requirements.

    So there it is. Now I haven't mentioned why in most synchronous logic systems we don't clock out on one edge and in on the other. That's because it halves your maximum clock frequency. And in a synchronous system where you're using the same technology and your clock tree is designed for minimum skew then you can, by design, guarantee not failing setup and hold time. SPI is meant to interface any arbitrary devices so it trades off maximum frequency for guaranteed setup and hold time.

No public wish lists :(