AndyP

Member Since: July 12, 2007

Country: United States

  • News - According to Pete - SPI a… | about 2 years ago

    Comments on your comments: Rise and fall times have nothing to do with setup and hold time.

    Rise and fall time tell you how fast the driver can transition a signal from one logic state to the other. The main reason to be concerned about these times is so that a signal doesn’t linger at an “undefined” level between valid logic states. This causes odd switching and can be a real problem on clock signals. Also, the faster the rise/fall time, the more you have to worry about signal integrity and termination and all of that. Note that rise and fall times are not special to SPI; they apply to ALL digital logic signals, synchronous or not.

    Setup time indicates when a data signal needs to be stable before a clock edge. Hold time indicates how long a data signal needs to remain stable after a clock edge. These parameters are critical for all synchronous logic circuits, including not only flip-flops but also synchronous memory elements (RAMs, ROMs, FIFOs). If it’s got a clock, it’s got setup and hold-time requirements.

    So the waveform displays which exaggerate the effect of rise and fall time and show you 10% and 90% levels are nice, but in the real world you just measure timing at the middle of the transition.

    Note that there’s a reason why SPI clocks data out on one edge and clocks it in on the other. It’s so you don’t have to deal with setup and hold time and driver clock-to-out calculations at all.

    Consider what some might call a “fast” SPI bus, with a 20 MHz (50 ns period) clock. Say the receiver has a setup time spec of 2 ns and a hold time spec of 2 ns. Say the driver has a clock to out time of 1 ns. If the driver and receiver were clocked on the same edges, then at clock edge 0, 1 ns later the data line transitions. At the same edge, the receiver looks at the input. Now a 1 ns clock-to-out means the signal is stable at the receiver 49 ns early (easily meeting setup) BUT it failed to meet hold time since it changed 1 ns after the clock but hold time says the receiver needs it stable 2 ns after the clock.

    Now clock in on the rising edge and out on the falling edge. 1 ns after the falling edge, the signal transitions (clock to out delay). With 2 ns setup time required at the receiver, you have 22 ns of slack (period - requirement - clock-to-out). Also, the signal is held at the receiver for 26 ns after the rising edge so you can’t fail hold-time requirements.

    So there it is. Now I haven’t mentioned why in most synchronous logic systems we don’t clock out on one edge and in on the other. That’s because it halves your maximum clock frequency. And in a synchronous system where you’re using the same technology and your clock tree is designed for minimum skew then you can, by design, guarantee not failing setup and hold time. SPI is meant to interface any arbitrary devices so it trades off maximum frequency for guaranteed setup and hold time.

No public wish lists :(