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January 24, 2013
about 6 months ago
Does anyone know how to fix this error when uploading to the ESp32 Thing with the Arduino IDE.
“A fatal error occurred: Failed to connect to ESP32: Timed out waiting for packet header”
thanks for any help
about 4 years ago
Really? So you have a list of requirements that cant be met by NIOSII running on my Altera chip or MicroBlaze running on my Xilinx chip, but can be meet by a M3 running as hardcore on the ASIC portion of my Cypress chip? Also I have worked with boards with analog inputs on soft core CPU’s on Spartan -3 and Spartan -6 FPGAs with ADC’s implemented in HDL so I dont know where you got that info from.
I didn’t see any tutorials , just a couple of videos on youtube, please post a link to these extensive tutorials if they exist, - thanks. The UnoProLogic has a nice price-point and it seems like a pretty cool device considering its fit with the arduino.
The Papilio has a AVR8 Soft Processor in the FPGA for use with their Arduino like IDE. Nice try though
“What separates this FPGA from the others is ease of use and the thorough tutorials that Embedded Micro provide”
….ummm no. As far as I can tell the tutorials are both pithy and fungible and add very little value. Its a shame the designers spent so much time on a product and seem to have missed what their target audience wants as hobbyists and basement engineers. A complet, hands-on learning experience with reconfigurable logic. My suggestion is spend 1% of the time you spent developing your board and make a real tutorial section otherwise you are giving us absolutely no reason to replace our Papilio’s with this product.
about 4 years ago
Hey Sleep, No you are exactly right, you have the option of coding HDL directly through the ISE Webpack, or c-style through the FPGA/Arduino IDE interpreted to the softcore processor.
Ive also been playing lately with the inexpensive DEO-Nano from Terasic. Its pretty cool as well. For that board you Use Alteras Quartus-II.
You can also use C/C++ style coding through the Xilinx SDK or Altera Nios. They both provide Eclipse customized plug-ins for their emulated soft-cores (Microblaze, AVR etc.). I cant speak to licensing cost issues on those products
There is a C/Processing/Arduino based IDE for this Papilio One board. I haven’t played with many coding examples for it through this IDE yet. However I would highly suggest you buy the Papilio board and buy The LogicStart Megawing. That particular wing comes with a free FPGA book and VHDL tutorial. You can follow it and program the board even if your HDL knowledge isn’t good using the free Xilinx WebPack ISE. Its the easiest board I have ever used when combined with Mike Fields(Hamsters) book and wing.
Having said that, your FPGA Language choices are pretty much VHDL/Verilog/SystemVerilog/SystemC whether you go with Xilinx’s ISE or Altera Quartus. Programming FPGAs is still in the explicit, low level state compared to MCU’s but that is slowly changing as resources and chip real estate becomes cheaper. Eventually FPGA semantics will closely resemble higher level programing code, just not yet.
I just want to reinforce what Member #257465 has said. If you are not a advanced FPGA user this board alone will do you very little good, its gonna sit their like a turd even if the code uploads due to its lack of on-board bells and whistles. Mike Fields, AKA Hamster has designed the LogicWing with a free tutorial (100+) pages witch is nothing short of excellent. I have fooled with other xilinx boards and the Papilio board with his logic wing along with his free book puts the other companies stuff to shame. SF really should sell the LogicWing with this board as a kit.
You can obviously use VHDL or Verlilog using any tool for this board. Hamster uses VHDL.
Quartus is the house Altera FPGA only tool, just as ISE is the Xilinx only house tool. This wont ever change. Third party tools are available from the big 3 (Cadence, Synopsis, Mentor Graphics) but start at thousands of dollars.
The Lattice and Mircosys/Actel also have their own FPGA free version house tools. Also as SGrace has pointed out, I wouldn’t even consider using open-source tools at this point with FPGA’s, very little chance you are going to generate a remotely viable bitfile.
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