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May 1, 2013
Product PGM-09825 |
It’s been a long time since looking at hardware specs, but in case someone is searching for the same information I am, I’d agree with TravisF, based on looking at the schematic/board layout (may2013) it seems sensitive 3.3V targets are ill-advised….I do not own this board currently, so I can’t verify the below, it comes from looking at the design docs.
1 - Cutting the trace between JP1 pins might work (disconnects from USB 5V power so entire board could be 3.3V powered, but you lose fuse protection on VCC, and a target may not be able to supply enough current)
However only 74AC125 buffers are spec’d to operate at 3.3V (schematic has 74ACT, while picture shows 74AC) Additionally, this presumes USB data signals will not cause issues on ATTINY if they end up at 5V…I found a reference that they were supposed to be 3V?
2 - Moving the switch to “not-powered” does not seem to prevent issues. Specifically as noted by TravisF/AffordableTechnology, CTL when driven from a 5V powered ATTINY will may either damage the 3.3V powered 74xx125 or leak through the 74xx125 & 22k (R10) to the target. If your device is 5V tolerant while running at 3V or not leaking much current through R10 you may not see problems.
Really what “not-powered” means in this context is USB power is not directly providing power to a target, and the 74xx125 buffer is powered by the target’s VCC. I would presume this is to avoid USB current limits more than to allow 3V compatibility.
3 - FYI if you’re considering cutting the CTL trace keep in mind that the 74xx125 is only spec’d to allow inputs VCC+0.5 so it could still be damaged by running it at 3V while the ATTINY is at 5V
So in short it seems to me that if you need to program a 3V sensitive device, you may wish to use a logic level shifter.
No public wish lists :(