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September 24, 2008
about 7 years ago
The pictures with rulers are not correct. The chip is 10mm square. The last time I checked, 10mm was still equal to 1cm and not a fraction thereof.
about 7 years ago
My message was too long and wouldn’t fit in one post…
Anyway, I don’t know the full consequences of overclocking the A/D block, but I’m guessing it’s not good. One of the KinetaMaps I bought has a completely non-functional A/D block and I’m wondering if it got fried.
Has anyone else noticed a problem with their ADC’s?
The KinetaMap firmware seems to be overclocking the A/D converters. See page 271 the LPC214x user manual (rev 02). The A/D clock should be 4.5 MHz or less. For this hardware setup the crystal oscillator is 12MHz. The PLLCFG register gets set to 0x24 in the bootloader code. Thus, the PLL multiplier is (4 + 1) or 5. The system clock (CCLK) is then 12MHz * 5 = 60MHz. The peripheral clock is also 60MHz because the APBDIV/VPBDIV register is set to 1.
Now, look at the code where the A/D converters are used:
AD1CR = 0x00200600 | channel;
This is the AD1 control register. You are setting the CLKDIV to be 0x06. Thus, the A/D clock is 60MHz / (6 + 1) = 8.57MHz! This is almost double the maximum recommended value. I’m guessing this code came from a Keil code sample where the APBDIV was set to 0x0 instead of 0x1, causing the peripheral clock to be ¼ of the system clock.
Since the APB clock is 60MHz, I recommend changing the aforementioned line of code to:
AD1CR = 0x00200E00 | channel;
This will result in a 4MHz A/D clock (60 / (14 + 1)).
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