Member Since: June 20, 2006

Country: United States

  • One of the big confusions that people have to keep in mind about VHDL is that unlike most “programming languages”, it’s not really designed for computers to parse. It’s more designed as a description language for documentation (for humans, or at least engineers) to read.

    At some point, computers got powerful enough for a subset of VHDL to be synthesizable, but at the core - the verbosity comes from the fact that humans and not computers were the original parsers of VHDL.

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