April 27, 2009
about 2 years ago
OK, figured it out… In the DRC rules, I changed the restring setting MIN to 4mm and 10% and it looks like it should. I guess it is another one of those stupid Eagle “features”, where the Design rule checker actually CHANGES the design.
This is odd, I must be running into some kind of Eagle bug or do not have something configured correctly… When I open the library, the footprint for the part looks good, no overlap of the solder pads and there is visible space between them. When in the schematic editor, I select the part using the “Add” function, the footprint has large pads that touch each other and causes the DRC errors. Weird…
Is this library correct? The Pads are touching each other and it fails DRC due to overlap.
about 6 years ago
I would so pay for this, but Boulder is out of the question… How about a teleconference or Webex version?
No public wish lists :(
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