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Member Since: October 5, 2009

Country: United States



Electrical Engineer/Enthusiast

Programming Languages



CMU, Oakland University


Microcontrollers / Sensors





  • That’s interesting. I just found out my Unos are the same way. Not sure why I never noticed this before. I assume they won’t change this and I’ll have to buy proto shields with the correct header spacing. At least they are not that expensive.

    Thanks for the info. Will Mega proto-shields have the right footprint as the Due boards? Just wondering if I can count on those working ;0)

  • Ok I’m looking for some help or an answer: I just realized that the Arduino Due pin spacing between the header with 8-13/GND/AREF/SDA1/SCL1 and the header with pins 0-7 are not aligned so one could use a 0.1 inch PCB as a shield. All other headers are aligned so it is possible, but its just the one with pins 8-13/GND/AREF/SDA1/SCL1 that does not fit.

    Any reason why? Is the Mega like this? Are they any ‘proto-shields’ that will work for all pins on this board?


  • When designing onto FPGAs, I’ve found that treating your implementations as ‘state-machines’ helps you figure out how to set everything up (design onto paper, splitting into a data-path and control unit, identify all states and transition conditions, determine how many registers and operations are needed etc.)

    The following link is a sample video of VHDL tutorials. https://www.youtube.com/watch?v=7N9mygI3A5o

    There are quite a few series of FPGA tutorials on youtube that explain things good. I remember one I used to use which was very helpful but cannot remember the name…so I’ll edit this post later once I find it.

    Going from any form of software design to designing for FPGA has a learning curve, but I think if you put the time into it you will begin to understand why VHDL and Verilog are the way they are. But hey, if all you want is the performance benefits and have a tool do it for you, some day it will exist. Each FPGA company has some version of ‘high level synthesis’ which converts C into verilog/vhdl. Xilinx even has tools for converting Simulink models into verilog (using their blocksets of course).

  • Not sure, since I did it in verilog (hence the poster’s question about using the PLD).Point being, it’s custom.

  • Cypress has a lot of ‘App notes’ with project examples on using these ICs. To give you a simple example of something I did with the PSOC4 in the PLD, I interfaced a rotary encoder to the ARM by configuring a filter and up/down counter in the PLD to keep track of the count as well as an interrupt signal to the ARM for roll-over detection. This was very simple, but it off-loaded a lot from the ARM’s point of view, since there was no need for ‘digital filtering’ nor processor interrupts on each pulse. So this was a custom hardware driver. The PSoC5 should be much more capable than the PSoC4 I believe.

    I thought the PSoC5 also had on-chip amplifiers you can use for signal processing. This is useful right? No need to wire up external circuity (other than perhaps resistors for gain control or filtering).

  • I would encourage those who use this board to move away from Arduino APIs. Cypress (if you use their IDE) has already developed useful APIs to use all of their peripherals. And yes, this is not an FPGA but the re-configurable ‘fabric’ is field-programmable (the ARM takes care of setting everything up by writing to the PLD’s configuration registers). Their IDE assists in the configuration of these registers through higher-level menus and other API-like features.

  • $49.95? Shouldn’t it bee…‘Free’? ;0)

  • By the way, if you (sparkfun) want to put something powerful out there…go Xylinx Zynq7000. Dual-core ARM microcontroller + FPGA on same IC. Tons of flexibility and power: https://www.digilentinc.com/Products/Detail.cfm?Prod=ZYBO

    You can even provide a sample bitstream with ‘arduino’ emulated on the FPGA to hook people in.

    I’d be interested in helping out.

  • I’ve used the PSoC4, not too shabby (especially for the cost). Wouldn’t really call it a full FPGA on the PSoC5, but it is nice to have some flexibility that does not involve CPU cycles. Imagine a ‘microcontroller’ with on-chip op-amps and configurable routing/logic to do custom tasks in parallel to the code running on your ARM processor.

    I’ve used the PSoC4 to make a self-balancing robot: http://ohmwardbond.blogspot.com/2014/12/self-balancing-robot.html

    Cool product!

  • I’m not so sure this is true. Stepper motors may have a constant current when it is holding a position (because the load is purely resistive during that time). When a there is some dynamic loading on the motor , there will be some transient change in current draw that should be seen in the phase windings. Not to mention, when the motor is actively being stepped, there will be transient currents during the active switching of the phase coils.

    A way to monitor the DC current used by a stepper motor, would be to measure before the switches (ie. monitor the current supply to the h-bridge V+ supply, assuming an h-bridge is used).