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Member Since: October 5, 2009

Country: United States



Electrical Engineer/Enthusiast

Programming Languages



CMU, Oakland University


Microcontrollers / Sensors





  • It really does get lonely during 2nd shift…How did you learn to manage this, lamp?

  • R&D of Light-saber prototyping trials, iteration # 41: Light more controlled than previous experiments. However, looking closer at our subject, we confirm consistent side-effect of hair removal from head and facial region.

  • This is a good example of the evolution of the amateur programmer: you ran into a hurdle and sought out a more efficient method, where you stumbled onto other hardware inside the machine you once thought you knew enough about; interrupts!

    Imagine what you could do once you learned about the other embedded features waiting to be uncovered! And yet, imagine the time period where these things had not yet existed on a single chip…if at all

    Always read your datasheets, and research certain parts of the micro, as they were put there for good reason,mostly stemmed from the long evolution of hardware and software.

    You may be interested in learning about other RTOS models out there

  • I did check the MinnowBoard Max, and I think I would rather choose that over the pcduino Acadia, especially since the cost is so close. And, it has a PCI-e port :0), it’s just not a quad-core :0(

  • Pros:

    • SATA is quite the advantage; you can store a lot of data there ;0) and even your OS can live there. You can have extra swap-space there when you run out of RAM.

    • The quad ARMv9 on the Acadia @ 1.2GHz obiously outperforms the raspi-2-B’s 900MHz quad ARMv7.

    • The Acadia’s onboard Wifi modul should outperform a USB-wifi dongle (but not entirely sure if that’s noticeable).
    • OpenGL! (raspi-2-B has a more proprietary graphics accelerator by Broadcom)


    • Need a USB hub for multiple devices while raspi-2-B has 4

    • 3x the $$$

    • 1GB RAM (so does raspi-2-B, but this is a big con for both I think)

  • That’s interesting. I just found out my Unos are the same way. Not sure why I never noticed this before. I assume they won’t change this and I’ll have to buy proto shields with the correct header spacing. At least they are not that expensive.

    Thanks for the info. Will Mega proto-shields have the right footprint as the Due boards? Just wondering if I can count on those working ;0)

  • Ok I’m looking for some help or an answer: I just realized that the Arduino Due pin spacing between the header with 8-13/GND/AREF/SDA1/SCL1 and the header with pins 0-7 are not aligned so one could use a 0.1 inch PCB as a shield. All other headers are aligned so it is possible, but its just the one with pins 8-13/GND/AREF/SDA1/SCL1 that does not fit.

    Any reason why? Is the Mega like this? Are they any ‘proto-shields’ that will work for all pins on this board?


  • When designing onto FPGAs, I’ve found that treating your implementations as ‘state-machines’ helps you figure out how to set everything up (design onto paper, splitting into a data-path and control unit, identify all states and transition conditions, determine how many registers and operations are needed etc.)

    The following link is a sample video of VHDL tutorials. https://www.youtube.com/watch?v=7N9mygI3A5o

    There are quite a few series of FPGA tutorials on youtube that explain things good. I remember one I used to use which was very helpful but cannot remember the name…so I’ll edit this post later once I find it.

    Going from any form of software design to designing for FPGA has a learning curve, but I think if you put the time into it you will begin to understand why VHDL and Verilog are the way they are. But hey, if all you want is the performance benefits and have a tool do it for you, some day it will exist. Each FPGA company has some version of ‘high level synthesis’ which converts C into verilog/vhdl. Xilinx even has tools for converting Simulink models into verilog (using their blocksets of course).

  • Not sure, since I did it in verilog (hence the poster’s question about using the PLD).Point being, it’s custom.

  • Cypress has a lot of ‘App notes’ with project examples on using these ICs. To give you a simple example of something I did with the PSOC4 in the PLD, I interfaced a rotary encoder to the ARM by configuring a filter and up/down counter in the PLD to keep track of the count as well as an interrupt signal to the ARM for roll-over detection. This was very simple, but it off-loaded a lot from the ARM’s point of view, since there was no need for ‘digital filtering’ nor processor interrupts on each pulse. So this was a custom hardware driver. The PSoC5 should be much more capable than the PSoC4 I believe.

    I thought the PSoC5 also had on-chip amplifiers you can use for signal processing. This is useful right? No need to wire up external circuity (other than perhaps resistors for gain control or filtering).