EEPROM2 Click provides 2 Mbit (2,097,152 bits) of Electrically Erasable and Programmable Read Only Memory, organized in bytes. In other words, this Click board™ is an EEPROM memory medium with the capacity of 256 KB. The used EEPROM module has an impressive endurance of 4,000,000 write cycles and data retention period of over 200 years. EEPROM module on this Click features an ESD protection. It also contains a memory page of 256 bytes, which can be permanently locked, once it is written. The Error Correction Code logic section ensures a reliable data output from the device.
EEPROM2 Click is aimed towards industrial and commercial applications, which require secure and reliable data storage. It can be used for any kind of temporary or permanent data storage for various embedded electronic devices, simple data logging, storing various working parameters of a module or device, sensitive data retention in case of a power cycle, and other similar applications where reliable EEPROM memory is needed.
The EEPROM module used on the EEPROM2 Click is the M95M02, an SPI serial EEPROM from STMicroelectronics, with the memory cell density of 2 megabits (Mbit). The EEPROM density is expressed in bits, so exactly 2,097,152 bits are organized in units or words of 8 bits, which gives 262,144 bytes of data memory. Furthermore, the EEPROM is organized in memory pages. One page holds 256 bytes and there are 1024 pages (1024 pages x 256 bytes = 262,144 bytes total). Having insight into how the memory cells are organized, is important for Write and Erase operations. The SPI pins are routed to the mikroBUS™ so the communication is easy and straightforward. The M95M02 IC supports clock frequency up to 5MHz.
This Click board™ uses the SPI communication protocol. To ensure reliable data transaction and to avoid accidental write to the memory array, the device employs certain protection mechanisms. When the M95M02 IC is powered up and when the power supply voltage reaches a certain threshold, the device will reset itself, setting up the internal logic in a known state. In addition, before writing any data to the IC which modifies registers or the array itself, the WEL bit must be set. This bit is cleared after or during every memory modification instruction. Therefore every memory modification instruction must be prefixed with the Write Enable instruction that sets this bit. This mechanism ensures that only the intended write instruction will be executed.
Communication with the device is initiated by the host MCU, which drives the chip select pin (#S on the schematic) to a LOW logic level. This pin is routed to the mikroBUS™ CS pin. The next byte of information can be either command or data. Usually, the first byte is the instruction (command) followed by the memory address. Depending on the command that has been sent, either the memory is written to, or read from the specific memory address. Memory address on this device is 18 bit (0x00000 to 0x3FFFF) and therefore it is sent by 3 bytes.
There are several instruction codes, which can be sent after the CS pin being driven to a LOW logic level. These include Write Enable and Disable, Write and Read from memory array, Read and Write to Status register, and so on. For a full list of commands, please refer to the datasheet of the M95M02 IC.
When using the Write to array instruction, it is possible to write up to 256 bytes in one write cycle. The internal address pointer is increased with each received byte. If attempting to write more than 256 bytes of data, a rollover will happen, writing the data from the beginning of the page. This is due to page organization of the memory array; only one full page can be written within a single write cycle.
The M95M02 includes a write protection of the specific parts or the whole memory array. The write protection consists of two bits in the Status Register (B0, B1), and the SRWD bit. The Status Register Write instruction can be used to set or reset these bits. B0 and B1 bits control the write-protect status of the memory array (from one quarter to full memory array protection). While the SRWD bit of the Status Register is set to 1, it is not possible to change the B0 and B1 bits. These bits are non-volatile and their state is retained between the power cycles.
One of the key features of the M95M02 IC is the Error Correction Code logic (ECC), which allows error correction by utilizing six additional bits, internally assigned to a group of four bytes. This protection scheme is capable of correcting some types of bit errors, staying transparent to the end user. The bit comparison and error correction are done internally.
Another feature of the M95M02 IC is an identification memory page, 256 bytes long. This page can be used to store an ID or other sensitive data, and once written, it can be permanently locked. The IC supports a set of instructions, used to perform the write, read and lock operation over this memory page.
EEPROM2 Click offers a selection between 3.3V and 5V operation, with the onboard SMD jumper, labeled as PWR SEL. This allows both 3.3V and 5V MCUs to be interfaced with this Click board™.
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