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We are constantly pushing ourselves for better printed circuit boards (PCB). One thing we've learned is that PCB fab houses (such as Advanced Circuits, BatchPCB, PCB123, Gold Phoenix, Bare Bones PCB, anyone really) have a very hard job to do. Creating a PCB is not an easy task and there are many ways for a fab house to mess it up. Unfortunately, fab houses tend to spend less time on prototypes than on production runs. Therefore, we try to design products and PCBs for 'manufacturability'. This tutorial will show you how to minimize the number of ways the fab house can screw up a PCB.
We've messed up piles of PCBs over the years. We want to share with you some of the DFM (design for manufacture) rules and tricks and tips we've learned to get a good PCB, every time. If you're creating a prototype PCB, we highly recommend you use these rules to increase the chances that your proto will work!
Trace Width and Spacing:
Just because a fab house can handle down to 5mil traces and 6mil space doesn't mean you should design with those sizes. If your board can be routed with 10mil traces and 10mil spaces, do it! The smaller you make things, the more likely you will get a PCB with broken trace (traces less than 10mil) or two traces touching each other (less than 10mil spacing between traces).
A ground (or power) plane is a good idea on some projects. But a plane (sometimes called a polygon plane) increases the odds of the plane being mistakenly 'poured' onto a trace.
We recommend you increase the default 10mil isolation in Eagle of a polygon pour to '0.012' or 12mil. This will pull the plane away from the signal traces, thus decreasing the odds of a manufacturing failure. This will however potentially break ground connections so be sure to check your rats nest!
Another problem that we have found is sloppy drill hits by a fab house. To connect a trace from one side of the PCB to the other, we use a via. A via is composed of a drilled hole, two circles of copper larger than the hole on either side of the board, and connecting copper inside the hole to connect the circles on either side of the board (these are called plated through holes). Vias make PCBs work. The problem is the size of the copper circles. If the drill hit is not in the middle of the circles, the drill hole can potentially break the via and the trace connected to the via.
Gerber File Generation:
Generating good gerber files of your PCB is the final step that causes many people to fail. Eagle uses a CAM file to create the gerber files to have a PCB made. We have seen tons of people create horribly defective gerber files. Please start with our CAM file - and modify if you really need to. We've used this CAM file thousands of times without problems.
We've changed the default Eagle CAM file so that it does not mirror any of the bottom layers (number one problem with gerber submissions!), it outputs a standard Excellon drill file (second most common error is a missing drill file), and captures only the tPlace layer onto the silkscreen layer (this will cause all part identifiers and values to not print on the silkscreen). Put all text and labels onto the tPlace layer that you want to see printed on the board.
Tenting refers to
the soldermask and vias. The vias on a board may be left exposed or
covered up by the soldermask. We've found that covering up the vias (or
'tenting' them) decreases the chances that the silkscreen labels will
be broken and gives the overall board a much better look. Don't worry,
you can still probe a tented via for voltage and continuity with a
multimeter - the soldermask will break down when you insert the probe
into the hole. However, it will be much more difficult to solder to a
Bottom view of the XBee-Explorer product. I have been known to move a via to avoid a label as well, but that's just me.
Tenting is taken care of in Eagle by modifying the DRC rules. To see if the vias will be tented or not, turn on all the layers by clicking on the display button:
on all the layers will create a lot of noise in the display of the
board. What you are looking for is the white hatch marks indicating
where the will be a lack of solder mask. The upper arrow points to a via that has no hatch marks, indicating there will be no lack of soldermask
on that via (tenting it). The lower arrow points to a large hole with a
white hatch mark on top of it. This is a solder point that needs to be
exposed. The white hatch marks indicate there will be a lack of solder mask over this hole, exposing it so that we can solder to it.
To tent your vias, open the DRC rules on your current design (Tools->DRC menu).
Then increase the limit value to larger than the vias you are using. For instance, if the vias on your board are the default 0.023mil, then change the limit to 25mil and all drill hits under 25mil (0.025) will be covered in soldermask. Be careful! Don't set this number too high or you will cover important holes, like those meant to solder on connectors. The DRC setting is set to 25mil in the SparkFun DRC file.
Label everything, all the time:
This is another cosmetic issue I see so often it hurts. You should label every button, switch, LED, pin, and especially power connectors on your board. Every one of them!