Alchitry Io Element Board

The Alchitry Io Element Board is the perfect way to get your feet wet with digital design. The Io features four 7-segment LEDs, five momentary push buttons, 24 basic LEDs, and 24 DIP switches that all lend themselves to fantastic beginner tutorials that will walk you through all the basics of FPGAs.

Alchitry Elements are expansion boards similar to shields for an Arduino or HATs for a Raspberry Pi but these are meant for your Au and Cu FPGA Development Boards. This Element is equipped with four connectors on the underside of the board that snap to an Au or Cu board. Be aware that the Io does not feature any connection points on the top of the board so you won't be able to stack any additional Elements on top of it.

  • 4x 7-segment LED digits
  • 5x momentary push buttons
  • 24x LEDs
  • 24x DIP switches

Alchitry Io Element Board Product Help and Resources

How Does an FPGA Work?

July 30, 2020

The What, How, Why, and When of Field Programmable Gate Arrays, aka FPGAs

First FPGA Project - Getting Fancy with PWM

July 30, 2020

An initial project using Alchitry's onboard FPGA to manipulate PWM

External IO and Metastability

July 30, 2020

Why external signals can cause metastability and how to use constraint files to manage this

Programming an FPGA

July 30, 2020

Come look at the basics of working with Field Programmable Gate Arrays.

Core Skill: Electrical Prototyping

If it requires power, you need to know how much, what all the pins do, and how to hook it up. You may need to reference datasheets, schematics, and know the ins and outs of electronics.

2 Electrical Prototyping

Skill Level: Rookie - You may be required to know a bit more about the component, such as orientation, or how to hook it up, in addition to power requirements. You will need to understand polarized components.
See all skill levels


Looking for answers to technical questions?

We welcome your comments and suggestions below. However, if you are looking for solutions to technical questions please see our Technical Assistance page.

  • Member #774403 / about 2 years ago / 1

    The LED groups and switches are backwards using io element base. Not sure about the led segments yet.

  • Member #1621132 / about 3 years ago / 1

    It is nice to have a board with switches and LEDs ready to go for this FPGA.

    BUT seriously, the switches are teensy tiny. I have to have my cheaters on, bright lights, and a specialized sharp switch flipper pointy device to flip them.

  • The push buttons and dip switches on the Io board aren't compatible with the Cu main board when stacked directly. The Io board switches and buttons connect the FPGA pin to VCC (through a resistor). The ice40 on the Cu main board doesn't have a pulldown option for the I/O buffer. Therefor, the state of the FPGA pins is either VCC or floating.

    There is a post on the Alchitry forums about this and they recommend swapping the pin between output low and input right before sampling it and hint that it might be fixed in a future revision.

    Another option is to use a Br board and some pulldown resistors, but it would be hard to fit them for all of the dip switches.

    • I realized I was looking at the schematic on the Alchitry website, which is for the old version of the board. However, on the new Sparkfun version, the pulldowns for the pushbuttons are in the wrong part of the circuit, and don't actually pull down the FPGA pin.

      • Ell C / about 4 years ago / 1

        We'll look into this ASAP. Thanks for the heads up!

Customer Reviews

2.5 out of 5

Based on 2 ratings:

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3 of 3 found this helpful:

Basic design flaw makes the switches unusable

The Lattice iCE40 HX FPGA used on the Alchitry Cu has internal pull-up (but not pull-down) resistors. Any input switches should therefore be connected between the FPGA I/O pins and the 0V line, with no external resistors required.

This board instead chooses to connect the switches between the FPGA I/O pins and +5V, thereby rendering the internal pull-up resistors unusable. This design choice would then require external pull-down resistors connected between the FPGA I/O pins and 0V, to ensure that the input is never left floating. However, this board instead pointlessly places its resistors in series between the switch and +5V.

The upshot is that the FPGA I/O pin is either at a logic high (weakly tied to +5V) when the switch is on, or undefined (left floating) when the switch is off. There is no physical state of the switch that will lead to a defined logic low input.

It is possible to work around this design flaw in Verilog by occasionally driving the input pin low, but this introduces an insanely unnecessary complexity into what should be a very basic function.

1 of 1 found this helpful:

Well designed product

Great build quality. The only issue is figuring out how to use it. Finding out the constraints is a major headache.